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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Presettable Counters
MC54/74HCT161A MC54/74HCT163A
High-Performance Silicon-Gate CMOS
The MC54/74HCT161A and HCT163A are identical in pinout to the LS161A and LS163A. These devices may be used as level converters for interfacing TTL or NMOS outputs to high speed CMOS inputs. The HCT161A and HCT163A are programmable 4-bit binary counters with asynchronous and synchronous reset, respectively.
16 1
J SUFFIX CERAMIC PACKAGE CASE 620-10
* * * * * * *
Output Drive Capability: 10 LSTTL Loads TTL, NMOS Compatible Input Levels Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 4.5 to 5.5 V Low Input Current: 1 A High Noise Immunity Characteristic of CMOS Devices
16 1 16 1
N SUFFIX PLASTIC PACKAGE CASE 648-08
In Compliance with the Requirements Defined by JEDEC Standard No. 7A * Chip Complexity: 200 FETs or 50 Equivalent Gates LOGIC DIAGRAM
D SUFFIX SOIC PACKAGE CASE 751B-05
ORDERING INFORMATION MC54HCXXXAJ MC74HCXXXAN MC74HCXXXAD 14 13 12 11 Q0 Q1 Q2 Q3 Ripple Carry Out BCD or Binary Outputs Device HCT161A HCT163A Count Mode Binary Binary Reset Mode Asynchronous Synchronous Ceramic Plastic SOIC
P0 Preset Data Inputs P1 P2 P3 Clock
3 4 5 6
2
15
Pinout: 16-Lead Package (Top View)
VCC RCO* 16 15 Q0 14 Q1 13 Q2 12 Q3 11 Enable T Load 10 9
Reset Load Count Enables Enable P Enable T
1 9 7 10 Pin 16 = VCC Pin 8 = GND
FUNCTION TABLE
Inputs Clock Reset* L H H H H Load X L H H H Enable P X X H L X Enable T X X H X L Output Q Reset Load Preset Data Count No Count No Count 1 2 3 P0 4 P1 5 P2 6 P3 7 8 Enable GND P
Reset Clock
* RCO = Ripple Carry Out
H = High Level; L = Low Level; X = Don't Care * = HCT163A only. HCT161A is an "Asynchronous-Reset" device.
10/95
(c) Motorola, Inc. 1995
1
REV 2
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MC54/74HCT161A MC54/74HCT163A
MAXIMUM RATINGS*
Symbol VCC Vin Parameter Value Unit V V V Positive DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) - 0.5 to + 7.0 - 1.5 to VCC + 1.5 - 0.5 to VCC + 0.5 20 25 50 750 500 Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA mA mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic or Ceramic DIP SOIC Package Storage Temperature Range mW Tstg TL - 65 to + 150 260 300
_C _C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
v
v
Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP or SOIC Package Ceramic DIP
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C Ceramic DIP: - 10 mW/_C from 100_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
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RECOMMENDED OPERATING CONDITIONS
Symbol VCC Parameter Min 4.5 0 Max 5.5 Unit V V DC Supply Voltage (Referenced to GND) Vin, Vout TA DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC - 55 0 + 125 500
_C
ns
tr, tf
DC ELECTRICAL CHARACTERISTICS (Voltages referenced to GND)
VCC V 4.5 5.5 4.5 5.5 4.5 5.5 4.5 4.5 5.5 4.5 5.5 5.5
Guaranteed Limit 85C 2.0 2.0 0.80 0.80 4.4 5.4 3.84 0.10 0.10 0.33 1.00 40 125C 2.0 2.0 0.80 0.80 4.4 5.4 3.70 0.10 0.10 0.40 1.00 160 Unit V V V
Symbol VIH VIL VOH
Parameter Minimum High-Level Input Voltage Maximum Low-Level Input Voltage Minimum High-Level Output Voltage
Test Conditions Vout = 0.1 V or VCC = -1.0V |Iout| 20 A
- 55 to 25_C 2.0 2.0 0.80 0.80 4.4 5.4 3.98 0.10 0.10 0.26 0.10 4
v v
Vout = 0.1 V |Iout| 20 A Vin = VIH or VIL |Iout| 20 A
v v v v
Vin = VIH or VIL |Iout| 4.0 mA VOL Maximum Low-Level Output Voltage Vin = VIH or VIL |Iout| 20 A Vin = VIH or VIL |Iout| 4.0 mA Iin ICC Maximum Input Leakage Current Maximum Quiescent Supply Current (Per Package) Additional Quiescent Supply Current Vin = VCC or GND Vin = VCC or GND Iout - 0 A Vin = 2.4V, Any One Input VIN = VCC or GND Other Inputs Iout - 0 A
V V V A A
ICC
-55C 2.9 5.5
25 to +125C 2.4 mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
MOTOROLA
2
High-Speed CMOS Logic Data DL129 -- Rev 6
MC54/74HCT161A MC54/74HCT163A
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V 10%: CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit Symbol fmax tPLH tPHL tPHL tPLH tPHL tPLH tPHL tPHL tTLH, tTHL Cin Maximum Propagation Delay Reset to Ripple Carry Out (HCT161A Only) Maximum Output Transition Time, Any Output Maximum Input Capacitance Maximum Propagation Delay Clock to Ripple Carry Out Maximum Propagation Delay Reset to Q (HCT161A Only) Maximum Propagation Delay Enable T to Ripple Carry Out Parameter Maximum Clock Frequency (50% Duty Cycle)* Maximum Propagation Delay Clock to Q Fig 1,7 1,7 1,7 2,7 3,7 3,7 1,7 1,7 2,7 2,7 1,7 - 55 to 25_C 30 20 25 25 16 21 22 28 24 15 10 85C 24 23 30 29 18 24 25 33 28 19 10 125C 20 28 32 33 20 28 28 35 32 22 10 Unit MHz ns ns ns ns ns ns ns ns ns pF
* Applies to noncascaded/nonsynchronous clocked configurations only. With synchronously cascaded counters, (1) Clock to Ripple Carry Out propagation delays, (2) Enable T or Enable P to Clock setup times, and (3) Clock to Enable T or Enable P hold times determine fmax. However, if Ripple Carry Out of each stage is tied to the Clock of the next stage (nonsynchronously clocked), the fmax in the table above is applicable. See Applications information in this data sheet. NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High- Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Gate)* 60 pF * Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
TIMING REQUIREMENTS (VCC = 5.0 V 10%: CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit Symbol tsu Parameter Minimum Setup Time, Preset Data Inputs to Clock Minimum Setup Time, Load to Clock Minimum Setup Time, Reset to Clock (HCT163A Only) Fig. 5 5 4 6 5 5 (HCT163A Only) 4 6 (HCT161A Only) 2 2 1 (HCT161A Only) 1 - 55 to 25_C 12 12 12 12 3 3 3 3 12 12 12 12 500 85C 18 18 18 18 3 3 3 3 17 17 15 15 500 125C 20 20 20 20 3 3 3 3 23 23 18 18 500 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Minimum Setup Time, Enable T or Enable P to Clock th Minimum Hold Time, Clock to Preset Data Inputs Minimum Hold Time, Clock to Load Minimum Hold Time, Clock to Reset Minimum Hold Time, Clock to En T or En P trec Minimum Recovery Time, Reset Inactive to Clock Minimum Recovery Time, Load Inactive to Clock tw Minimum Pulse Width, Clock Minimum Pulse Width, Reset tr, tf Maximum Input Rise and Fall Times
High-Speed CMOS Logic Data DL129 -- Rev 6
3
MOTOROLA
MC54/74HCT161A MC54/74HCT163A
FUNCTION DESCRIPTION
The HCT161A/163A are programmable 4-bit synchronous counters that feature parallel Load, synchronous or asynchronous Reset, a Carry Output for cascading and count-enable controls. The HCT161A and HCT163A are binary counters with asynchronous Reset and synchronous Reset, respectively. INPUTS Clock (Pin 2) The internal flip-flops toggle and the output count advances with the rising edge of the Clock input. In addition, control functions, such as resetting and loading occur with the rising edge of the Clock input. In addition, control functions, such as resetting (HCT163A) and loading occur with the rising edge of the Clock Input. Preset Data Inputs P0, P1, P2, P3 (Pins 3, 4, 5, 6) These are the data inputs for programmable counting. Data on these pins may be synchronously loaded into the internal flip-flops and appear at the counter outputs. P0 (Pin 3) is the least-significant bit and P3 (Pin 6) is the most-significant bit. OUTPUTS Q0, Q1, Q2, Q3 (Pins 14, 13, 12, 11) These are the counter outputs. Q0 (Pin 14) is the least-significant bit and Q3 (Pin 11) is the most-significant bit. Ripple Carry Out (Pin 15) When the counter is in its maximum state 1111, this output goes high, providing an external look-ahead carry pulse that may be used to enable successive cascaded counters. Ripple Carry Out remains high only during the maximum count state. The logic equation for this output is: Ripple Carry Out = Enable T * Q0 * Q1 * Q2 * Q3 H L X X Load CONTROL FUNCTIONS Resetting A low level on the Reset pin (pin 1) resets the internal flip- flops and sets the outputs (Q0 through Q3) to a low level. The HCT161A resets asynchronously, and the HCT163A resets with the rising edge of the Clock input (synchronous reset). Loading With the rising edge of the Clock, a low level on Load (pin 9) loads the data from the Preset Data input pins (P0, P1, P2, P3) into the internal flip-flops and onto the output pins, Q0 through Q3. The count function is disabled as long as Load is low. Count Enable/Disable These devices have two count-enable control pins: Enable P (Pin 7) and Enable T (Pin 10). The devices count when these two pins and the Load pin are high. The logic equation is: Count Enable = Enable P * Enable T * Load The count is either enabled or disabled by the control inputs according to Table 1. In general, Enable P is a count-enable control: Enable T is both a count-enable and a Ripple-Carry Output control. Table 1. Count Enable/Disable Control Inputs Enable Enable P T H H L X H H H L Result at Outputs Q0-Q3 Count No Count No Count No Count Ripple Carry Out High when Q0-Q3 are maximum* High when Q0-Q3 are maximum* L
Q0 through Q3 are maximum when Q3 Q2 Q1 Q0 = 1111. OUTPUT STATE DIAGRAM
0 1 2 3 4
15
5
14
6
13
7
12
11
10
9
8
Binary Counters
MOTOROLA
4
High-Speed CMOS Logic Data DL129 -- Rev 6
MC54/74HCT161A MC54/74HCT163A
SWITCHING WAVEFORMS
tr Clock 90% 1.3V 10% tw 1/fMAX tPLH Any Output 90% 1.3V 10% tTLH tTHL tPHL Any Output tf 3.0V Reset GND tPHL 1.3V trec Clock 1.3V GND 1.3V GND tw 3.0V
3.0V
Figure 1.
Figure 2.
tr Enable T tPLH Ripple Carry Out 90% 1.3V 10% tTLH 90% 1.3V 10%
tf 3.0V Reset GND tPHL Clock tTHL tsu 1.3V GND th 1.3V GND 3.0V 3.0V
Figure 3.
Figure 4. HCT163A Only
Inputs P0, P1, P2, P3 tsu Load tsu Clock
3.0V 1.3V GND th 3.0V 1.3V th 1.3V GND GND trec 3.0V Clock Valid Enable T or Enable P 3.0V 1.3V GND tsu th 1.3V GND 3.0V
Figure 5.
Figure 6.
TEST POINT OUTPUT DEVICE UNDER TEST CL*
*Includes all probe and jig capacitance
Figure 7. Test Circuit
High-Speed CMOS Logic Data DL129 -- Rev 6
5
MOTOROLA
MC54/74HCT161A MC54/74HCT163A
14 Q0
P0
3
T0 R C C Load Load P0
Q0
Q0
P1
4
T1 R C C Load Load P1
13 Q1
Q1
Q1
P2
5
T2 R C C Load Load P2
12 Q2
Q2
Q2
P3
6
T3 R C C Load Load P3
11 Q3
Q3
15 Ripple Carry Out Enable P 7
Enable T
10
Reset
1
R Load Load
Load
9
Clock
2
C C
The flip-flops shown in the circuit diagrams are Toggle- Enable flip-flops. A Toggle-Enable flip-flop is a combination of a D flip-flop and a T flip-flop. When loading data from Preset inputs P0, P1, P2 and P3, the Load signal is used to disable the Toggle input (Tn) of the flip-flop. The logic level at the Pn input is then clocked to the Q output of the flip-flop on the next rising edge of the clock. A logic zero on the Reset device input forces the internal clock (C) high and resets the Q output of the flip-flop low.
Figure 8. 4-Bit Binary Counter with Asynchronous Reset (MC54/74HCT161A)
MOTOROLA
6
High-Speed CMOS Logic Data DL129 -- Rev 6
MC54/74HCT161A MC54/74HCT163A
Reset (HCT161A) Reset (HCT163A) Load P0 P1 P2 P3 Clock (HCT161A) Clock (HCT163A) Enable P Enable T Q0 Q1 Outputs Q2 Q3 Ripple Carry Out 12 13 14 15 0 Count 1 2 Inhibit (Asynchronous) (Synchronous)
Preset Data Inputs
Count Enables
Reset
Load
Figure 9. Timing Diagram
High-Speed CMOS Logic Data DL129 -- Rev 6
7
MOTOROLA
MC54/74HCT161A MC54/74HCT163A
14 Q0
P0
3
T0 R C C Load Load P0
Q0
Q0
P1
4
T1 R C C Load Load P1
13 Q1
Q1
Q1
P2
5
T2 R C C Load Load P2
12 Q2
Q2
Q2
P3
6
T3 R C C Load Load P3
11 Q3
Q3
15 Ripple Carry Out Enable P 7
Enable T
10
Reset
1
R Load Load
Load
9
Clock
2
C C
The flip-flops shown in the circuit diagrams are Toggle- Enable flip-flops. A Toggle-Enable flip-flop is a combination of a D flip-flop and a T flip-flop. When loading data from Preset inputs P0, P1, P2 and P3, the Load signal is used to disable the Toggle input (Tn) of the flip-flop. The logic level at the Pn input is then clocked to the Q output of the flip-flop on the next rising edge of the clock. A logic zero on the Reset device input forces the internal clock (C) high and resets the Q output of the flip-flop low.
Figure 10. 4-Bit Binary Counter with Synchronous Reset (MC54/74HCT163A)
MOTOROLA
8
High-Speed CMOS Logic Data DL129 -- Rev 6
MC54/74HCT161A MC54/74HCT163A
TYPICAL APPLICATIONS CASCADING
Load Inputs Inputs Inputs
Load H=Count L=Disable H=Count L=Disable Enable P Enable T Clock Reset Reset
Q0 Q1 Q2 Q3 Ripple Carry Out Q0 Q1 Q2 Q3
Load Enable P Enable T Clock Reset
Q0 Q1 Q2 Q3 Ripple Carry Out Q0 Q1 Q2 Q3
Load Enable P Enable T Clock Reset
Q0 Q1 Q2 Q3 Ripple Carry Out Q0 Q1 Q2 Q3 To More Significant Stages
Outputs Clock
Outputs
Outputs
NOTE: When used in these cascaded configurations the clock fmax guaranteed limits may not apply. Actual performance will depend on number of stages. This limitation is due to set-up times between Enable (port) and clock.
Figure 11. N-Bit Synchronous Counters
Inputs Load Enable P Enable T
Inputs
Inputs
Load Enable P Enable T Clock Clock Reset Reset
Q0 Q1 Q2 Q3 Ripple Carry Out Q0 Q1 Q2 Q3
Load Enable P Enable T Clock Reset
Q0 Q1 Q2 Q3 Ripple Carry Out Q0 Q1 Q2 Q3
Load Enable P Enable T Clock Reset
Q0 Q1 Q2 Q3 Ripple Carry Out Q0 Q1 Q2 Q3 To More Significant Stages
Outputs
Outputs
Outputs
Figure 12. Nibble Ripple Counter
High-Speed CMOS Logic Data DL129 -- Rev 6
9
MOTOROLA
MC54/74HCT161A MC54/74HCT163A
TYPICAL APPLICATIONS VARYING THE MODULUS
HCT163A Other Inputs Q0 Q1 Q2 Q3 Reset Reset Optional Buffer for Noise Rejection Output HCT163A Other Inputs Q0 Q1 Q2 Q3 Optional Buffer for Noise Rejection Output
Figure 13. Modulo-5 Counter
Figure 14. Modulo-11 Counter
The HCT163A facilitates designing counters of any modulus with minimal external logic. The output is glitch- free due to the synchronous Reset.
MOTOROLA
10
High-Speed CMOS Logic Data DL129 -- Rev 6
MC54/74HCT161A MC54/74HCT163A
OUTLINE DIMENSIONS
-A -
16 9
J SUFFIX CERAMIC PACKAGE CASE 620-10 ISSUE V
-B - C L
1
8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIM F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. INCHES MIN MAX 0.750 0.785 0.240 0.295 -- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 15 0 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 -- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 15 0 1.01 0.51
-T
SEATING - PLANE
N E F G D 16 PL 0.25 (0.010)
M
K M J 16 PL 0.25 (0.010)
M
TB
S
TA
S
DIM A B C D E F G J K L M N
-A -
16 9
N SUFFIX PLASTIC PACKAGE CASE 648-08 ISSUE R
B
1
8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MILLIMETERS MIN MAX MIN MAX 0.740 0.770 18.80 19.55 6.35 0.250 0.270 6.85 3.69 0.145 0.175 4.44 0.39 0.015 0.021 0.53 1.02 0.040 0.070 1.77 0.100 BSC 2.54 BSC 0.050 BSC 1.27 BSC 0.21 0.008 0.015 0.38 2.80 0.110 0.130 3.30 7.50 0.295 0.305 7.74 0 0 10 10 0.020 0.040 0.51 1.01
F S
C
L
-T - H G D 16 PL 0.25 (0.010)
M
SEATING PLANE
K
J TA
M
M
-A -
16 9
D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
-B -
1 8
P 8 PL 0.25 (0.010)
M
B
M
G F
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019
K C -T SEATING -
PLANE
R X 45
M D 16 PL 0.25 (0.010)
M
J
T
B
S
A
S
High-Speed CMOS Logic Data DL129 -- Rev 6
11
MOTOROLA
MC54/74HCT161A MC54/74HCT163A
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
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MOTOROLA
CODELINE
*MC54/74HCT161A/D*
12
MC54/74HCT161A/D High-Speed CMOS Logic Data DL129 -- Rev 6

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